鲁汶仪器来yl23455永利进行学术合作交流

报告题目：集成电路中low-k材料的应用及挑战

With the aggressive scaling of advanced integrated circuits to deep sub-micron levels, the signal delay caused byinterconnects became increasingly significant compared to the delay caused by the gate. In addition, the cross talk noise and power dissipation became much more important in circuit performance. To reduce the resistance-capacitance (RC) delay, the industry has replaced the Al conductor by Cu(lowering resistance) and Silicon Dioxide (SiO2) by materials with a lower dielectric constant, low-k(lowering capacitance). In order to reduce the dielectric constant of a material, either atomic groups with a small polarizability can be inserted or the electronic density can be lowered. The density has a stronger effect on the k-value than the polarizability, since the density can be lowered till zero (air-gaps), achieving unity as k-value. The ultra low-k materials introduction in Cu technology has been much slower than anticipated in the ITRS Roadmap. The introduction of porosity in low-k materials has increased the level of complexity tremendously. In this presentation, the challenges appearing during the integration of ultra low-k dielectrics will be discussed, since a proper understanding of these issues is essential for downscaling of the interconnect system. The extreme vulnerability of porous low-k to processing -induced damage (accompanied with the loss of dielectric performance and reliability) demands a continuous innovation of materials, processes and integration approaches. Recently developed new materials and innovation solutions for low-k integration will also be discussed.